Digital communication systems require accurate clock recovery or clock synchronisation techniques to achieve the lowest possible bit error rate in the received information. In Time Division Multiple Access (TDMA) systems information is communicated in specific time slots. In burst-mode TDMA systems, the transceiver of the digital communication system transmits on one time slot and receives on another: for example, in the Digital European Cordless Telecommunications system (DECT) the transceiver transmits on the first time slot and receives on the thirteenth. Since information is only communicated at set time intervals, it is particularly important that accurate clock synchronisation is achieved.
Typically, a synchronisation word precedes the data to be received so that the transceiver clock has a very short period during the synchronisation word in which to synchronise itself to the following data.
The ability of the transceiver to synchronise its clock accurately to the received data has a significant affect on the overall system performance and its ability to recover the received data accurately. If the transceiver clock and received data are unsynchronised, errors can be introduced on decoding of the received data. This is highlighted in noisy conditions. Thus, accurate clock synchronisation techniques are required to achieve the lowest possible bit error rate in the received data signal.
Present burst-mode TDMA systems, such as the CT-2 system which has a data rate of 72Kbit/s, use clocks having frequencies which are faster than the received data rate, for example 16, 32 or even 64 times faster: the transceiver clock generates the clock signal on receiving the first transition of the synchronisation word. Since the clock signal is not generated until the first transition is received, there is an error in the synchronisation. This error is acceptable for low data rate systems such as the CT-2 system. However, for higher data rate systems over 100Kbit/s, such as DECT having a data rate of 1.152Mbit/s, such an error may not be acceptable so that expensive and/or power consuming crystals and control circuitry are required in order to produce a fast enough clock signal to achieve a reasonable bit error rate.
Another method of achieving clock synchronisation in burst-mode communication systems includes utilising phase-lock circuits. However, phase-lock techniques can require significant space and power and this increases as the data rate gets higher. This would be a major disadvantage in transceivers for use in portable communications products. Furthermore, burst-mode communications systems would require complex phase-lock circuits which increases the cost of such systems.
A software controlled method may also be used to achieve clock synchronisation in burst-mode communications systems. However, as the system data rates increase, the software implementation becomes extremely complex and requires the use of expensive and power consuming microprocessors and a substantial amount of memory. As with large, power consuming phase-lock circuits, the space and power of such circuits would be a major disadvantage for transceivers for portable communications products.
Accordingly, the invention seeks to provide an improved clock synchronisation circuit and method of synchronising a clock signal in which the above problems of the prior art are mitigated.